In semiconductor memory device manufacturing, the channel length of the DRAM transfer gate devices continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for low leakage DRAM transfer devices. There is thus a need for novel integration schemes with only limited shrinking of the channel length.
As the DRAM cell size decreases, the transfer gate has consequently shrunk with it. Earlier cell sizes (&gt;8 F.sup.2) allow for wiggled gates to keep the array transistor off leakage to a minimum. With the onset of 8 F.sup.2 cells with equal lines and spaces at minimum feature size, F, in the wordline direction, there is need to provide larger transfer gate lengths of the array pass transistor by non-lithographic techniques. Conventional scaling techniques use shallow junctions (limited by surface leakage and charge writeback characteristics), high channel doping concentrations or halo implants which increase leakage and are thus not easy to incorporate in DRAM processing.
One known process is based on the BEST (BuriEd Strap) cell modified for 8 F.sup.2. Once the trench capacitor and shallow trench isolation are formed, the gate conductor stack is put down. Typically, the gate conductor stack consists of polysilicon and WSi.sub.x capped with SiN. During the gate mask opening step, the SiN is patterned and the etch typically stops in the WSi.sub.x, the resist is stripped and the remaining gate conductor stack is etched with the SiN as a hard mask. Post gate sidewall oxidation, the SiN spacers are formed, followed by a barrier SiN film and boron phosphorus silicate glass (BPSG) deposition, densification and planarization. A TEOS (tetraethylorthosilicate) layer is formed for the damascene bitlines and the bitline contacts are etched borderless to the gates prior to forming the bitline wiring layer (generally tungsten).
Additionally, it is known that the present processing of DRAM structures in the array portion of the device directly links the lithographic dimension to the polysilicon linewidth. Hence, if there is resist webbing, the increase in the polysilicon linewidth is limited which directly affects the retention of the DRAM cell.
The present invention is thus directed to further improvements in gate conductor processing which can be easily incorporated into existing DRAM processing techniques.